Frame phase aligner

Abstract

A frame phase aligner for a transfer system includes selection circuitry for selecting one of a plurality of input signal groups, which include data, a clock signal, an inverse clock signal and a frame synchronous signal, received from outside of the frame phase aligner. A selection signal generator provides the selection circuitry with a selection signal according to write data input from outside of the frame phase aligner, so that the selection circuitry selects one of the plurality of input signal groups according to the selection signal indicative of the setup environment of the transfer system. A control signal generator generates control clock signals and a retiming control signal in order to demultiplex selected data of the input signal group selected. A demultiplexer demultiplexes data selected to form parallel data, retimes the parallel data, and controls the phase of the parallel data according to the control retiming signal and the control clock signals output from the control signal generator. A multiplexer synchronizes the demultiplexed data output from the demultiplexer to a reference frame synchronous signal and reference control signals, and a reference control signal generator provides the reference frame synchronous signal and the reference control signals for the multiplexer.