Partitioned decode circuit for low power operation

Abstract

A partitioned decoder circuit responds to an address signal supplied at a decoder circuit input by providing a result data signal that corresponds to the address signal. Selection signal decoder circuitry asserts one or more of a plurality of decoder enable signals based upon the value of a decoder selection signal. A plurality of decoder circuit elements are each connected to receive a separate one of the asserted decoder enable signals. Each decoder circuit element includes a first clock input coupled to receive a precharge clock signal, an address input coupled to receive the address signal, address latching circuitry that latches the address signal in response to a polarity transition of the precharge clock signal, and a second clock input. Significantly, gated discharge clock signal generation circuitry of each decoder circuit element generates a gated discharge clock signal in response to the asserted decoder enable signal. The gated discharge clock signal is provided to the second clock input. A data output responds to the gated discharge clock signal being provided to the second clock input by providing an evaluation signal that corresponds to the latched address signal such that the result data signal includes the evaluation signal.