The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 13, 1996
Filed:
Oct. 30, 1995
Robert A Pease, San Francisco, CA (US);
Robin Shields, Inverclyde, GB;
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
A protection circuit for a semiconductor switch for switching a load is disclosed. Control circuitry is used for switching the semiconductor switch on in response to a switching signal and for switching the semiconductor switch off in response to a deactivation signal. A deactivation circuit is used for generating the deactivation signal. An overvoltage detector circuit responsive to a voltage at an output of the semiconductor switch that exceeds a predetermined value is used for generating an overvoltage signal. The overvoltage detector circuit includes a Zener diode that has its cathode coupled through a resistor to the output of the semiconductor switch and its anode coupled to the collector of the diode connected transistor. A first logic circuit is used for causing the deactivation circuit to generate the deactivation signal in response to the switching signal and the overvoltage signal. The first logic circuit includes a first npn transistor that has its base coupled through a resistor to receive the switching signal. A second npn transistor receives the overvoltage signal through a resistor at its base. The collector of the first npn transistor is coupled to the collector of the second npn transistor. A third npn transistor has its base coupled to the collector of the second npn transistor. A first pnp transistor has its base coupled to the collector of the third npn transistor. One of the two collectors is coupled to the deactivation circuit.