The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 13, 1996

Filed:

Jun. 30, 1995
Applicant:
Inventor:

Gregg D Croft, Palm Bay, FL (US);

Assignee:

Harris Corporation, Melbourne, FL (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
327310 ; 327582 ; 361111 ;
Abstract

A monolithic voltage clamp provides low impedance, low voltage electrostatic discharge protection for an integrated circuit without affecting the integrated circuit's DC characteristics. First, second, third, and fourth regions of semiconducting material are formed with p-n junctions between each region. A first inductor electrically connects the first and second regions, and a second inductor electrically connects the third and fourth regions. The first and second inductors should each have an inductance which is large enough to delay an increase in bypass current around their respective p-n junctions for a period which is long enough to assure that conduction is sufficient to discharge an electrostatic pulse. In a preferred embodiment, first and second reverse bias diodes are used to electrically connect the invention to one or more input/output nodes. In another embodiment, an integrated circuit having first and second potential inputs, and a plurality of input/output nodes, may be provided with a transient clamp according to the invention. Along with the first and second reverse bias diodes used to connect the invention to one or more input/output nodes, third, fourth, fifth, and sixth reverse bias diodes may be used to electrically connect the first and second potential inputs to respective first and fourth semiconducting regions. In this configuration, an input/output node can operate at voltages above and below supply voltages provided to the first and second potential inputs, limited only by the breakdown voltages of the third and fourth reverse bias diodes.


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