The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 13, 1996
Filed:
Feb. 17, 1995
Fuyuki Okamoto, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
A latch circuit with an NAND function comprises a three-input NAND gate circuit, a first transfer gate connected between a first input terminal and a first input of the NAND gate circuit, a second transfer gate connected between a second input terminal and a second input of the NAND gate circuit, and a third transfer gate connected between a third input terminal and a third input of the NAND gate circuit. An input of a feedback inverter is connected To an output of the NAND gate circuit, and an output of the feedback inverter is connected to the first input of the NAND gate circuit through a fourth transfer gate. The second and third inputs of the NAND gate circuit are pulled up to a logical high level through P-channel MOS transistors. The first, second, third and fourth transfer gates and the P-channel MOS transistors are controlled by a clock signal in such a manner that when the first, second and third transfer gates are on, the fourth transfer gate and the P-channel MOS transistors are off, so that the NAND gate circuit performs a NAND operation in response to input signals applied to the first, second and third input terminals, and when the first, second and third transfer gates are off, the third transfer gate and the P-channel MOS transistors are on, so that a latch operation is performed to maintain a logical value on the output of the NAND gate circuit.