Static logic circuit with improved output signal levels

Abstract

A static logic circuit with improved output signal levels includes a static complementary MOSFET circuit with a signal node and pull-up and pull-down amplifiers, each with at least one biasing circuit, connected thereto. The pull-up and pull-down amplifiers are connected to VDD and VSS, respectively, and receive one or more logic signals (e.g. one for an inverter and more for logic gates such as AND, OR, etc.) and one or more bias signals and in accordance therewith provide pull-up and pull-down voltages, respectively, to the signal node. In accordance with the applied pull-up or pull-down voltage, the signal node charges to a charge state with an associated node voltage approximately equal to VDD or VSS, respectively. Each biasing circuit receives the same input logic signal as its associated pull-up or pull-down amplifier and provides thereto a bias signal approximately equal to VSS or VDD, respectively. In accordance with its input logic signal, each pull-up or pull-down amplifier together with its associated biasing circuit provides either an active current path between the signal node and VDD or VSS for applying the desired pull-up or pull-down voltage, respectively, or a leakage current path between VDD and VSS for preventing the application of an undesired pull-down or pull-up voltage during application of the desired pull-up or pull-down voltage, respectively.