The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 13, 1996

Filed:

May. 13, 1994
Applicant:
Inventor:

Risho Koh, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437 89 ; 437 40 ; 437913 ; 437180 ;
Abstract

On the substrate of an integrated circuit chip is deposited a first insulating layer in which a low resistivity semiconductor region is subsequently formed. An insulating film is formed on a side wall of the low resistivity semiconductor region. A slit is formed in the first insulating layer so that a portion of the substrate and a portion of the insulating film are exposed. First, second and third semiconductor layers of different conductivity types are epitaxially grown in the slit so that the second layer is in contact with the exposed insulating film. A second insulating layer is deposited on the chip. Through the second insulating layer first, second and third electrodes are brought into contact with the first and third semiconductor layers and with the low resistivity semiconductor region. Due to the stacking of epitaxial layers of different conductivity types, the impurity profiles of the epitaxial layers can be precisely controlled.


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