The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 06, 1996

Filed:

Dec. 22, 1994
Applicant:
Inventors:

Toshio Doi, Kokubunji, JP;

Takehisa Hayashi, Sagamihara, JP;

Kenichi Ishibashi, Hachioji, JP;

Takeshi Takemoto, Sagamihara, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
395445 ; 395456 ; 395459 ; 364D / ;
Abstract

A method of controlling a cache memory disposed between a CPU and a main memory, wherein pairs of data and an address to be written in the cache memory are stored into a buffer memory. A plurality of pairs of data and an address read from the buffer memory are processed to compare the address fields thereof. Based on results of the comparisons, there is determined a write control for writing the data in the cache memory which has been subdivided into a plurality of banks. As a result, the plural pairs of data and an address are written into the plural banks of the cache memory, the addresses of the respective pairs being different from each other. With the provisions set forth above, the write operation can be independently conducted for each bank of the cache memory, thereby improving the write throughput.


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