The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 06, 1996
Filed:
Oct. 18, 1994
Applicant:
Inventors:
Joseph A Casasanta, Allen, TX (US);
Bernhard H Andresen, Dallas, TX (US);
Yoshinori Satoh, Plano, TX (US);
Stanley C Keeney, Dallas, TX (US);
Robert C Martin, Dallas, TX (US);
Assignee:
Texas Instruments Incorporated, Dallas, TX (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03D / ;
U.S. Cl.
CPC ...
375376 ; 370108 ; 327149 ; 327150 ;
Abstract
A device and method for reducing phase jitter in digital phase locked loop applications resulting in smaller clock skews between application specific integrated circuits (ASICs). Phase jitter is reduced by a fine resolution digital delay line (20) comprising both coarse stages (variable delay element 24) for rough/fast phase adjustment and fine stages (fine resolution delay element 22) for precise delay adjustment when phase lock is near.