The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 06, 1996

Filed:

May. 24, 1995
Applicant:
Inventor:

Reiko Sumida, Mine, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
257707 ; 257 691 ; 257700 ; 257706 ; 257713 ; 257774 ;
Abstract

A semiconductor ceramic package includes a plurality of laminated insulator layers each formed from a ceramic. A semiconductor chip mounting portion is formed on a surface insulator layer. A power plane is formed on at least one of internal insulator layers. A ground plane is also formed on at least one of internal insulator layers. A plurality of thermal vias are formed beneath the semiconductor chip mounting portion. Each thermal via includes a first thermal via formed so as to transmit heat generated by a semiconductor chip mounted on the semiconductor chip mounting portion to the side of a back surface layer and a second thermal via formed so as to transmit the heat generated by the semiconductor chip to the side of the back surface layer. The first thermal via is connected to the power plane and the second thermal via is connected to the ground plane. The first and second thermal vias are formed to be adjacent to each other.


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