The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 06, 1996
Filed:
Dec. 01, 1994
Robert W Tsang, Bedford, MA (US);
Jeffrey A Farash, Holbrook, MA (US);
Richard S Payne, Andover, MA (US);
Analog Devices, Inc., Woburn, MA (US);
Abstract
A method for providing a conductive ground plane beneath a suspended microstructure. A conductive region is diffused into a substrate. Two dielectric layers are added: first a thermal silicon dioxide layer and then a silicon nitride layer. A first mask is used to etch a ring partially through the silicon nitride layer. Then, a second mask is used to etch a hole through both dielectric layers in a region having a perimeter that extends between the inner and outer edges of the ring. This leaves the conductive region exposed in an area surrounded by a ring that has the silicon dioxide layer and a narrow silicon nitride layer. The ring is surrounded by an area in which the silicon dioxide and silicon nitride layers have not been reduced. A spacer silicon dioxide layer is deposited over the dielectric and then a polysilicon layer is deposited and formed into the shape of a the suspended microstructure. When the spacer layer is etched away, the silicon dioxide under the narrow silicon nitride layer is removed, along with the narrow silicon nitride layer, leaving an exposed ground plane surrounded by a dielectric with minimal undercutting.