The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 30, 1996

Filed:

Dec. 22, 1993
Applicant:
Inventors:

George S Taylor, Menlo Park, CA (US);

P Michael Farmwald, Berkeley, CA (US);

Timothy P Layman, San Carlos, CA (US);

Huy X Ngo, Santa Clara, CA (US);

Allen W Roberts, Union City, CA (US);

Assignee:

Silicon Graphics, Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B06F / ;
U.S. Cl.
CPC ...
395403 ; 395417 ; 395445 ; 395449 ; 36424341 ; 36424345 ;
Abstract

A two-level cache memory system for use in a computer system including two primary cache memories, one for storing instruction and one for storing data. The system also includes a secondary cache memory for storing both instructions and data. The primary and secondary caches each employ their own separate tag directory. The primary caches use a virtual addressing scheme employing both virtual tags and virtual addresses. The secondary cache employs a hybrid addressing scheme which uses virtual tags and partial physical addresses. The primary and secondary caches operate in parallel unless the larger and slower secondary cache is busy performing a previous operation. Only if a 'miss' is encountered in both the primary and secondary caches does the system processor access the main memory.


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