The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 30, 1996
Filed:
Oct. 19, 1994
Scott C Petler, Rocklin, CA (US);
Hewlett-Packard Company, Palo Alto, CA (US);
Abstract
Logic to determine the current state of an output encoded finite state machine is minimized. Specifically, in order to generate logic for a finite state machine, input is received from a user. The input specifies states of the finite state machine, transition conditions between states and output values for each state. For example, a graphical user interface is used to receive a graphic portrayal of a state diagram. Logic is generated which implements the finite state machine from the inputs received by the interface means. Particularly, a plurality of flip-flops is generated. A first set of flip-flops is for storing output for the finite state machine. A second set of flip-flops is used, when necessary, with the first set of flip-flops to uniquely identify each state. When output values of the first set of flip-flops uniquely identify each state, the second set of flip-flops is not used (i.e., the second set of flip-flops is the null set). For each state, a combination of a minimum number of the flip-flops from the first set of flip-flops and the second set of flip-flops is detected which uniquely identifies the state.