The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 30, 1996
Filed:
Jan. 31, 1995
Mahesh N Ganmukhi, Wexford, PA (US);
Brian L Jordan, Pittsburgh, PA (US);
Fore Systems, Inc., Warrendale, PA (US);
Abstract
The present invention pertains to an apparatus for manipulating ATM cells. The apparatus comprises a memory array in which an entire ATM cell can be read or written in one read or write cycle. The apparatus is also comprised of a mechanism for reading or writing the entire ATM cell from or into the memory array. The present invention pertains to a method for switching an ATM cell. The method comprises the steps of receiving the ATM cell at a first input port of a switch from the ATM network. Then there can be the step of storing the ATM cell in one clock cycle in a memory array of the switch. Next there is the step of reading the ATM cell in the memory array in one clock cycle. Next there is the step of transferring the ATM cell from the memory array to a first output port of the switch. Next there is the step of transmitting the ATM cell from the first output port to the ATM network. The present invention pertains to a switch for an ATM cell. The switch comprises I input ports which receive ATM cells from an ATM network, where I>1 and is an integer. The switch is also comprised of a memory array connected to the I input ports for storing an ATM cell received by one of the I input ports in one clock cycle. The switch also comprises O output ports connected to the memory array, where O>1 and is an integer. One of the O output ports transmit an ATM cell which is received from the memory array to the ATM network. Additionally, the switch comprises a controller connected to the memory array, I input ports and O output ports for controlling the storage of an ATM cell from one of the input ports into the memory array in one clock cycle. The switch can be used for normal switching operation, multicasting, demultiplexing or multiplexing.