The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 30, 1996

Filed:

Jul. 21, 1994
Applicant:
Inventors:

Yutaka Kozai, Tokyo, JP;

Kiyoto Watabe, Hyogo, JP;

Tatsuhiko Ikeda, Hyogo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257513 ; 257519 ; 257520 ; 257374 ;
Abstract

It is an object of the present invention to provide a semiconductor device which has a high electrical isolation capability and an enhanced electrical reliability for avoiding short circuit of individual conductive layers, and the present invention also provides a method of manufacturing such a semiconductor device. An n.sup.+ buried layer and an n.sup.- epitaxial growth layer are formed on a p.sup.- silicon substrate. An element isolation oxide film having a through hole is formed on the surface of n.sup.- epitaxial growth layer. A trench which penetrates through n.sup.- epitaxial growth layer and n.sup.+ buried layer to reach a predetermined depth of p.sup.- silicon substrate is formed under through hole. A first insulating layer covers the internal wall of trench. A covering layer covers the sidewall of through hole. A filling layer is formed to fill trench so that the top surface thereof is located within through hole. A second insulating layer is formed on filling layer.


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