The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 23, 1996
Filed:
Jun. 07, 1995
Shingo Kojima, Tokyo, JP;
NEC Corporation, , JP;
Abstract
The present invention provides an input buffer circuit which prevents, when a microprocessor reads an external data bus upon bus sizing, a microprocessor from fetching an intermediate potential of the external data bus. READY terminal 3 is connected to one of a pair of input terminals of NOR gate 12 via latches 7 and 8, and lower data input terminal 4 is connected to the other input terminal of NOR gate 12. The output terminal of NOR gate 12 is connected to a data input terminal of data latch 14. SZRQ terminal 2 is connected to one of a pair of input terminals of NAND gate 10 via latches 5 and 6, and the output of latch 8 is connected to the other input terminal of NAND gate 10 via inverter 9. The output terminal of NAND gate 10 and upper data input terminal 1 are connected to input terminals of NOR gate 11, and the output terminal of NOR gate 11 is connected to an input terminal of data latch 13. Output terminals of data latches 13 and 14 serve as output terminals of the input buffer circuit.