The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 1996

Filed:

Oct. 05, 1992
Applicant:
Inventors:

George D Zuras, Jr, San Jose, CA (US);

Alexander J Neudeck, Fort Collins, CO (US);

Assignee:

Hewlett-Packard Company, Palo Alto, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
371 371 ;
Abstract

A method and circuit allows for generating syndrome bits from a plurality of data bits and a plurality of correction bits. The plurality of data bits are divided into subsets. From each subset of data bits, a plurality of syndrome bit partial products are generated using a logic gate tree, for example of XOR logic gates or XNOR logic gates. Each logic gate tree generates a syndrome bit partial product for each syndrome bit. The syndrome bits are generated from the syndrome bit partial products and from the correction bits, for example using XOR logic gates or XNOR logic gates. Within each logic gate tree, logic gates are arranged in rows. Each row of logic gates is used to generate a syndrome bit partial product for at least one syndrome bit.


Find Patent Forward Citations

Zuras, Jr, George. (1996). Method and circuitry for generating syndrome bits within an error (U.S. Patent No. 5539754). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5539754

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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