The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 1996

Filed:

Dec. 16, 1993
Applicant:
Inventors:

Tsutomu Nomoto, Hachioji, JP;

Hideki Kamada, Hachioji, JP;

Ichiro Ohno, Hachioji, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G02F / ; G02F / ; H01L / ; H01L / ;
U.S. Cl.
CPC ...
359 59 ; 359 87 ; 257 59 ;
Abstract

A plurality of address wiring layers and a plurality of data wiring layers are arranged to cross each other at a right angle. TFTs are respectively arranged at the intersections between the address wiring layers and the data wiring layers. The gate electrode of each TFT is connected to an address wiring layer for each row. The drain electrode of each TFT is connected to a data wiring layer for each column. Display electrodes are respectively arranged in the regions defined by the address wiring layers and the data wiring layers, and are connected to the source electrodes of the TFTs arranged in the respective regions. The data wiring layers and the source and drain electrodes of the TFTs each comprise the first layer serving as an ohmic barrier layer for a semiconductor layer, the second layer forming of a conductive material and serving as a main signal wiring layer, and the third layer serving as a battery reaction preventing layer.


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