Dot clock generation with minimal clock skew

Abstract

A dot clock generation system has a voltage-controlled oscillator (VCO) for generating a dot clock signal for an analog-to-digital convertor (ADC). A dot clock synchronization (sync) generator counts cycles of the dot clock signal and generates a dot clock sync signal. An analog video signal is passed through a first differential buffer to create an analog video sync signal. The analog video sync signal is passed through a first flip-flop storage element to a phase detector. The dot clock sync signal is passed through a second storage element and then through a second differential buffer to the phase detector. The second storage buffer insures that the edge of the dot clock sync signal which is used by the phase detector is tightly tied with the sampling edge of the dot clock signal which is used by the ADC to sample the analog data within the analog video signal. Moreover, the first and second buffers and storage elements introduce similar propagation time delays into the analog video sync signal and the dot clock sync signal. Accordingly, the phase detector accurately compares the phases of these sync signals and generates a highly accurate voltage control signal for the voltage-controlled oscillator, thereby resulting in a high precision dot clock signal.