The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 1996

Filed:

Mar. 25, 1993
Applicant:
Inventors:

Takeshi Sugoh, Yokosuka, JP;

Hisashi Sugiyama, Yokohama, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
257207 ; 257500 ; 257203 ;
Abstract

A semicustom integrated circuit comprises pads arranged on peripheral portions of a chip along the four sides thereof. Peripheral circuit cells are arranged on a part of the chip to the inside of the pads. An internal circuit is arranged on a part of the chip to the inside of the peripheral circuit cell. The peripheral circuit cells include an ECL level input circuit an ECL level output circuit, a TTL level input circuit and a TTL level output circuit. Main source lines are formed on the peripheral circuit cells so as to surround the internal circuit. The main source lines are connected to pads to which source potentials is applied. Branch source lines cross the main source lines and connected to a selected one of the peripheral circuit cells and said internal circuit. The main source lines are selectively connected to the branch source lines by an interlayer connecting source line.


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