Data repacking circuit having toggle buffer for transferring digital

Abstract

A method implemented in hardware logic for transforming data from one bus dth to another includes the steps of: 1) selectively latching data having p1 words each having a q1 width, where p1 and q2 are positive integers; and 2) selectively buffering the latched data as p2 words each having q2 bits, where p1q1=p2q2, and p2 and q2 are positive integers. The present invention also provides an electrical circuit for transforming a series of data having a first width into a series of data having a second width. A toggle buffer having a plurality of data latches selectively latches data having p1 words each having a q1 width, and buffers the latched data as p2 words each having q2 bits, where p1q1=p2q2, and p1, p2, q1, and q2 are positive integers. An input selector is coupled to the toggle buffer so as to provide a series of latching strobes to a first sequence of the latches. The input selector directs the data to be stored as p1 words, each word having q1 bits. An output selector is coupled to the toggle buffer for selectively enabling a second sequence of the latches so as to direct the toggle buffer to buffer the stored data as p2 words, each word having q2 bits.