Expandable memory for a digital signal processor including mapped first

Abstract

A data processing and addressing unit for processing a set of either first or second type instructions having associated therewith operands stored in a single memory bank and operands stored in two memory banks, respectively. First and second memory banks are mapped in continuous memory address space such that a bottom address of the second memory bank is contiguous with a top address of the first memory bank. A method is employed for mapping the first and second memory banks so as to permit memory expansion or contraction while permitting the first and second memory banks to be configured as a single continuous buffer or as two distinct buffers, as required. According to the method, the first memory bank is mapped as a negative offset with respect to the bottom address of the second memory bank such that the top address of the first memory bank has an offset of -1 and a bottom address thereof has an offset of -(first size); and the second memory bank is mapped as a positive offset with respect to the bottom address of the second memory bank such that a top address thereof has an offset of (second size - 1). Expansion or contraction of the first and second memory banks may thus be effected relative to a common boundary between the two memory banks and independent of their respective sizes.