The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 16, 1996
Filed:
Mar. 05, 1993
Marvin D Bausman, Chippewa Falls, both of, WI (US);
Vernon W Swanson, Chippewa Falls, WI (US);
Cray Research, Inc., Eagan, MN (US);
Abstract
A clock distribution system minimizes clock skew in the distribution of clock signals to individual circuit board components in a highly synchronous, high speed computer system. The clock system includes an optical subsystem and an electrical subsystem. The optical subsystem utilizes multiple lasers and an n.times.n passive star coupler to introduce clock redundancy into the system. The lengths of the optical distribution fibers are controlled such that they are of equivalent optical path length. Once delivered to the logic assemblies, the optical clock signals are converted into equivalent electrical clock signals. The electrical subsystem then distributes the converted electrical clock signals to individual circuit board components over equalized fanout paths such that the skew as seen by the individual components is minimized. The system also compensates for skew introduced by the receiver and fanout electronics by tuning the length of the fiber. The electrical subsystem further includes means for customizing the fanout to fit individual circuit boards such that extraneous system noise is reduced. The overall clock system results in a maximum clock distribution network skew of approximately .+-.100 picoseconds, thus reducing or eliminating the need to perform electrical deskew at the individual circuit board components.