Convolutional interleaver with reduced memory requirements and address

Abstract

A convolutional interleaver and addressing scheme where up to B consecutive symbols containing errors can be interleaved such that they are separated from each other by at least N intervening symbols. Memory, such as RAM, is configured with (B-1) cells of increasing size for storing symbols from a data stream. A first one of the cells has M storage locations which store M symbols. Each successive one of the cells has M more storage locations than the immediately preceding cell for storing M more symbols than the immediately preceding cell, where M=N/B. The cells are successively addressed to write a next symbol from the stream into a next write symbol location in a currently addressed cell and to read a symbol from the location of the currently addressed cell immediately following the next write symbol location. The locations are accessed in a first revolving manner such that the last location in a cell is followed by the first location in that cell. The cells are addressed in a second revolving manner such that the (B-1)th cell is followed by the first cell, or vice versa. An intervening transfer stage between the (B-1)the cell and the first cell to directly transfers the next symbol to the interleaver output. Each consecutive symbol from the stream is written into a next consecutive one of the cells. A deinterleaver has the same structure.