The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 16, 1996
Filed:
Nov. 30, 1994
Pradip Banerjee, San Jose, CA (US);
Atul V Ghia, San Jose, CA (US);
Patrick Chuang, Cupertino, CA (US);
Sony Corporation of Japan, Park Ridge, NJ (US);
Sony Electronics, Inc., Park Ridge, NJ (US);
Abstract
The method and apparatus of the present invention provides an interface between a testing device and a random access memory (RAM). The RAM comprises two types of RAM, a TAG RAM and a data RAM. In normal operation, the TAG RAM is not coupled to any devices external to the RAM. Thus, to test the TAG RAM, means must be provided to couple the testing device with the RAG RAM. One possible configuration for interface the TAG RAM with the testing device is to dedicate a line from the testing device to the TAG RAM for each output pin of the testing device, which significantly increases the size of the chip. To reduce this increase in size, according to the present invention, the write lines from the testing device share the bus used by the TAG RAM during normal operation. A multiplexer selects between the testing data and normal address data to insure the integrity of data over the bus. By sharing lines according to the present invention, a TAG RAM may be interfaced to a testing device with a minimum expansion of chip size.