The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 09, 1996
Filed:
Jun. 09, 1994
Motorola, Inc., Schaumburg, IL (US);
Abstract
A processor (50) is coupled to a plurality of peripherals (56 and 58) via an address bus (54) and a data bus (52). The peripherals (56 and 58) contain base address registers (BARs) (68 and 70). The peripherals (56 and 58) are either identical peripherals or similar peripherals wherein the BARs (68 and 70) are addressed via the same address within the system. In order to allow for each peripheral (56 and 58) to be written with a unique BAR value (in order to allow each peripheral to have a separate and distinct address space), the storage devices (64 and 66) are provided. When a data value is sent on the data bus (52) which has a set D0 bit and a cleared D1 bit, the device (64) is set to an asserted state and the device (66) is set to a deasserted state. This asserted state on device (64) allows the BAR (68) to be written on the next write operation if the address provided via address bus (54) corresponds to the BARs (68 and 70) while device (66) preempts BAR (70) from being written due to it's deasserted state. This method can be used for systems with no BARs and for N peripherals wherein N is a finite integer greater than zero.