The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 09, 1996
Filed:
Jan. 20, 1995
Derwin W Mattos, Sunnyvale, CA (US);
James D Shiffer, II, Fremont, CA (US);
Jeffrey F Wong, Fremont, CA (US);
VLSI Technology, Inc., San Jose, CA (US);
Abstract
An I/O buffer is provided that is noise-isolated, i.e., less susceptible to the effect of switching noise. In particular, a noise isolated I/O buffer includes an output terminal, a transient switching circuit connected to first power and ground voltage sources, to a logic input signal and to the output terminal, and a logic holding circuit connected to second power and ground voltage sources separate from the first power ground voltage sources, to the logic input signal and to the output terminal. The transient switching circuit causes a logic level of the output terminal to be switched responsive to a change in the input signal. The logic holding circuit causes the logic level of the output terminal to be maintained in the absence of a change in the input signal. In the absence of a change in the input signal, the transient switching circuit may be turned off, therefore presenting a high impedance to the first power and ground voltage sources. Switching noise in the first power supply network therefore is not transmitted through to the outputs of unswitched I/O buffers. The transient switching circuit and the logic holding circuit may be connected to the same power and ground voltage sources. The transient switching circuit, however, is turned off in the absence of a change in the input signal, and the logic holding circuit is turned off responsive to a change in the input signal. Smaller current surges are therefore provided at different times rather than a single large current surge, thereby reducing dI/dt. Provision is made for delaying turn on of the logic holding circuit until a logic transition of the output signal is substantially complete, further reducing the effects of switching noise on unswitched outputs. Preferably, the logic holding circuit, once it has been turned on, remains on despite possible changes in the output voltage level and is turned off only in response to changes in the input signal. The transient switching circuit may be constructed so as to, once it has been turned off, remain off despite possible changes in the output voltage level, or to turn back on in order to help return to output voltage to the proper level.