The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 02, 1996
Filed:
Apr. 18, 1994
Roger E Tipley, Houston, TX (US);
Compaq Computer Corporation, Houston, TX (US);
Abstract
A computer system including the peripheral component interconnect (PCI) bus, including the LOCK# and STOP# signals and also having an extra sideband signal for supporting posted read transactions. The extra sideband signal, referred to as POST#, is used in conjunction with the LOCK# and STOP# signals defined in the PCI specification to implement the posted read. A posting target that determines that its read cycle is a long latency read, where the PCI bus should be released for non-exclusive accesses in the interim, asserts the STOP# and POST# signals to disconnect or retry the master and initiate a posted read. The master asserts the LOCK# signal in response to lock the posted target for the posted read, and then rearbitrates the PCI bus to other masters. Other masters may then access the PCI bus and perform non-exclusion access in the interim, while the posted target fetches the requested data. Masters requiring locked cycles or access to the posted target are disconnected or retried, or the cycle is otherwise aborted. Eventually, the original posting master regains control of the PCI bus, re-asserts the locked access and retrieves the data from the posted target.