The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 02, 1996

Filed:

Feb. 10, 1994
Applicant:
Inventors:

Gregory M Smith, Colorado Springs, CO (US);

Michael W Yeager, Colorado Springs, CO (US);

J Donald Pauley, Estes Park, CO (US);

Gary T Carroll, Boulder, CO (US);

Assignee:

Racom Systems, Inc., Englewood, CO (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03D / ;
U.S. Cl.
CPC ...
375334 ; 375335 ; 329300 ; 329302 ;
Abstract

An integrated FSK detector circuit includes a first counter that receives a carrier signal and provides a multiple-bit output for reducing the frequency of the carrier signal into a plurality of weighted sub-multiples. An oscillator enable decoder circuit provides predetermined calibrate and measure pulses in response to the first counter output. A gated oscillator receives the calibrate and measure pulses and provides a burst of oscillator pulses during these time intervals. A second counter has an input coupled to the output of the gated oscillator and an up/down control terminal coupled to the output of the first counter. The output of the second counter also provides a multiple-bit output for reducing the frequency of the gated oscillator pulses. An FSK decoder logic circuit decodes the multiple-bit output of the second counter into a single bit FSK detect signal. The FSK detector circuit also includes a reset circuit coupled to the first counter for resetting between FSK detections.


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