The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 02, 1996
Filed:
Nov. 10, 1994
Yasushi Sato, Kawasaki, JP;
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
This invention relates to a J-K flip-flop circuit which achieves a decrease in area required on an integrated circuit and a reduction of cost. Three N-MOSFETs, whose gates respectively receive a clock CL1, a J signal, and a signal from one node of a second flip-flop circuit, are connected in series with each other, and one end of this series connection is connected to one node of a first flip-flop circuit. Three N-MOSFETs, whose gates respectively receive the clock CL1, a K signal, and a signal from the other node of the second flip-flop circuit, are connected in series with each other, and one end of this series connection is connected to the other node of the first flip-flop circuit. Two N-MOSFETs, whose gates respectively receive a clock CL2 and a signal from one node of the first flip-flop circuit, are connected in series with each other, and one end of this series connection is connected to the other node of the second flip-flop circuit. Two N-MOSFETs, whose gates respectively receive the clock signal CL2 and a signal from the other node of the first flip-flop circuit, are connected in series with each other, and one end of this series connection is connected to one node of the second flip-flop circuit. The other end of each of these series connections is connected to a ground voltage.