The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 02, 1996
Filed:
Nov. 24, 1993
Naofumi Kondo, Nara, JP;
Mikio Katayama, Ikoma, JP;
Masaya Okamoto, Soraku-gun, JP;
Makoto Miyago, Higashiosaka, JP;
Kiyoshi Nakazawa, Fujiidera, JP;
Yuzuru Kanemori, Nara, JP;
Makoto Tachibana, Nara, JP;
Sharp Kabushiki Kaisha, Osaka, JP;
Abstract
This invention provides an inspecting method, an inspecting apparatus, and a defect correcting method, for an active matrix substrate including: a gate bus line; a source bus line; a pixel electrode; a switching element for driving the pixel electrode; and a pair of electrodes constituting an auxiliary capacitance. The inspecting method includes: a step of disposing a counter substrate having a face on which a counter electrode is formed so that the face faces the active matrix substrate with a liquid crystal layer interposed therebetween, and connecting signal supplying terminals to gate bus lines and source bus lines and the counter electrode; and a detection step of detecting a defect on the active matrix substrate by performing at least one of a first signal generating step, a second signal generating step, and a third signal generating step. The first, second, and third signal generating steps all include alternately applying an ON signal for turning on the switching element and an OFF signal for turning off the switching element to the gate bus line. The first signal generating step includes applying a first detecting signal having a voltage which changes before the ON signal is applied to the source bus line. The second signal generating step includes applying a second detecting signal having a voltage which changes before and after the ON signal is applied. The third signal generating step includes applying a third detecting signal having a voltage which changes after the ON signal is applied.