The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 02, 1996
Filed:
Feb. 15, 1995
Michael P Weir, Ballston Lake, NY (US);
Hunt A Sutherland, Saratoga Springs, NY (US);
General Electirc Company, Schenectady, NY (US);
Abstract
A system for testing the integrity of critical circuitry, lines and wires employs a differential amplifier having an input resistance R.sub.in and a feedback loop with a resistance R.sub.fb. The critical wires being tested must be a signal wire series connected to a resistance R.sub.s, which is in turn series connected to a return wire. A test voltage source is connected to the noninverting input of the differential amplifier. The signal wire is connected to the inverting input of the differential amplifier. The test voltage source is activated by a test control unit. When activated, the test voltage source provides two distinct outputs allowing computation of a test gain in the presence of other functional signals. The test control unit measures the output V.sub.out of the differential amplifier and computes the value of the test gain. A break in either the signal wire or the return wire will result in a test gain of 1. If the signal and return wires are shorted, the test gain will be 1+R.sub.fb /R.sub.in. If the wires are undamaged, the test gain will be 1+R.sub.fb /(R.sub.in +R.sub. s). The test control unit then activates an appropriate output device in the event of a fault. In an alternate embodiment, a second amplifier is employed to synthesize a second signal which is subtracted out of the V.sub.out signal to remove the effects on the signal introduced from testing.