Processor failure detection and recovery circuit in a dual processor

Abstract

A dual processor computer system is disclosed that includes a processor failure detection and recovery circuit which initially designates one of the processing units as the lead-off master and the other processing unit as a slave. The processor failure detection and recovery circuit includes a timer unit which begins the countdown of a predetermined period in response to the initial resetting of the master and slave processors. The processor failure and detection circuit further includes a control unit which determines whether the master processor fails to reset or suffers from a hard failure by determining whether a bit of a storage unit has been set in response to software code intended for execution by the master processor during initialization. If the bit is not set before the lapse of the predetermined time period following reset, the control unit changes the designation of the slave processor to master and simultaneously resets the re-designated master. The control unit further holds the failed processing unit in an inactive state.