Hierarchical structure processor having at least one sub-sequencer for

Abstract

A hierarchical structure processor including a memory for storing processing instruction code data described sequentially; a main CPU for fetching and decoding the processing instruction code data and generating an executing sequence, the main CPU having buses for transferring instructions, data control signals; and a plurality of sub CPUs connected to the main CPU through the buses for executing basic instructions received from the main CPU. The main CPU includes a bus controller for sending a macro instruction indicative of the basic processing to one of the sub CPUs and for receiving an execution result of the processing designated by the macro instruction from the sub CPU. The bus controller waits for a READY signal from the associated sub CPU having the execution result. Each of the sub CPUs includes an execution unit for decoding the macro instruction received from the main CPU into one or more micro instructions for execution; a holding unit for holding an execution result obtained through execution of the plurality of micro instructions; and a READY signal unit for providing the READY signal to one of the buses when sending the execution result to the holding unit for receiving the result. At least one of the sub CPUs has additional buses for transferring instructions, data and control signals, and the hierarchical structure processor further comprises at least one CPU element connected to the additional buses for executing at least part of the micro instructions under control of at least one of the sub CPUs.