Circuit arrangement for a clock generator

Abstract

To ensure error-free transmission of digital information, very stringent requirements are placed on the accuracy and stability of the clock generators. It is known to use microprocessor-controlled digital phase-locked loops for this purpose, which contain costly high-stability crystal oscillators. An accurate system clock signal is to be provided even if the reference clock signal fails. Contradictory requirements are placed on the phase-locked loops, namely, on the one hand, a wide bandwidth to achieve a small time interval error, and, on the other hand, a narrow bandwidth to minimize the effect of jitter and wander on clock accuracy if the reference clock signal should fail. The invention provides a circuit arrangement for a low-cost clock generator which generates a highly accurate clock frequency even in the event of a failure of the reference clock signal. According to the invention, the contradictory requirements placed on a phase-locked loop are divided between two phase-locked loops which are both controlled by a microprocessor and have only one fixed-frequency generator associated with them. A first phase-locked loop (1) with a narrow bandwidth is connected via a switch (3) to a second, wide-bandwidth phase-locked loop. If the reference clock signal fails, the output of the first phase-locked loop (1) will be switched as an internal reference clock to the second phase-locked loop (2).