The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 25, 1996
Filed:
Oct. 26, 1994
Akiyoshi Kudo, Hyogo, JP;
Kazuo Hayashi, Hyogo, JP;
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Abstract
A compound semiconductor device includes a carrier supply layer supplying free charge carriers and having high dopant impurity concentration regions with a prescribed width, disposed in stripe shapes along a main current flow direction, parallel to each other, and spaced at an interval, and a carrier channel layer to which free charge carriers are supplied from the carrier supply layer including an electron channel having a high free carrier density at portions corresponding to respective high dopant impurity concentration regions of the carrier supply layer in the vicinity of a heterojunction interface. The heterojunction interface formed by the carrier channel layer and the carrier supply layer has a periodic undulating shape with convex portions and valley portions in stripe shapes extending parallel to the main current flow direction. A pseudo one-dimensional electron channel is formed in the vicinity of the high dopant impurity concentration region of the carrier supply layer whereby electron mobility is increased. The regions other than the high dopant impurity concentration regions of the carrier supply layer have a low dopant impurity concentration whereby the charge carrier quantity and output per unit chip area are increased, thereby increasing power output without increasing chip area.