The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 25, 1996
Filed:
May. 01, 1995
Wojciech B Kosmowski, San Juan Capistrano, CA (US);
John M Rudolph, Carlsbad, CA (US);
Cybernetics Products, Inc., Santa Ana, CA (US);
Abstract
A system and method for optimizing drill coordinates in a multi-layer printed circuit board, to correct for interlayer shift during lamination. A set of test patterns, in the form of a cross formed by two orthogonal conductor lines, are defined at each corner of each layer in the same nominal location. Under ideal conditions, the test patterns of the layers in each corner are lined up one above the other, without any offset. A counter sinking tool is used to cut a conical bore in the location of the test patterns, so that every test pattern cross is interrupted in four places, generating a four segment pattern in each layer. A high resolution camera is placed above the countersunk bore to form a single image of the exposed segment edges of all the test patterns exposed by the bore. The image is analyzed to determine the amount of shift of each layer. If all patterns are perfectly concentric, all crosses are perfectly aligned. By measuring the shift of each pattern from the nominal position, the amount of shift in each layer is determined. The process is repeated for the test patterns at each corner of the board, and the resultant layer shift data is processed to optimize the drilling pattern for the board.