The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 18, 1996

Filed:

May. 24, 1995
Applicant:
Inventor:

Sathyanandan Rajivan, San Jose, CA (US);

Assignee:

Sun Microsystems, Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03D / ;
U.S. Cl.
CPC ...
375376 ; 375374 ;
Abstract

An inventive apparatus for generating a plurality of phase-shifted clocks on an IC, including a PLL disposed at a first location for generating a reference clock and a reference voltage, local clock generation circuit disposed at a second location, and a first conductor coupling to both the PLL and the local clock generation circuit for furnishing the reference clock from the PLL to the local clock generation circuit. The inventive apparatus further includes a second conductor coupling to both the PLL and the local clock generation circuit for furnishing the reference voltage from the PLL to the local clock generation circuit; wherein the plurality of phase-shifted clocks are generated at the second location, responsive to the reference voltage and the reference clock, using the local clock generation circuit.


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