Pipelined decoder for high frequency operation

Abstract

A decoder for decoding a serial data stream employs an extracted base clock signal, synchronous with an input, coded, serial data stream, a first fractionary frequency clock signal for sampling a decoded output data stream and a second fractionary frequency clock signal for synthesizing a pre-decoded value, produced by a first combinative logic network, within a second combinative logic network to produce a decoded value that is sent to an output sampling flip-flop. In a decoder according to the present invention, a pipelined operation is implemented by momentarily storing the bits (part of the bits handled by the decoder) that are processed in the second combinative logic network and by anticipating of two full cycles of the synchronous base clock signal the processing, by said first combinative network, of the total n-number of bits handled by the decoder. Each one of the two combinative logic networks is permitted to complete its decoding process within a full clock cycle in advance of the rising front of the output sampling clock signal. With the same fabrication technology and therefore with the same propagation delay of the two combinative logic networks, the maximum operating speed may be doubled. A limited number of additional components are required to implement the pipelined operation of the invention.