The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 18, 1996
Filed:
Oct. 03, 1994
Edward H Honnigford, Russiaville, IN (US);
Delco Electronics Corporation, Kokomo, IN (US);
Abstract
A voltage clamping circuit is provided for clamping the input voltage to CMOS devices near the rail voltages so as to prevent forward biased junctions, minority carrier injection and crosstalk between voltage inputs. The voltage clamping circuit receives an input voltage and provides an output voltage within a rail-to-rail voltage range. The clamping circuit has a bias circuit with a PMOS device for providing a p-channel threshold drop to an upper rail voltage so as to generate an upper threshold bias voltage. The bias circuit also has an NMOS device for providing an n-channel threshold increase to a lower rail voltage so as to generate a lower threshold bias voltage. A first clamping transistor is coupled to the input for clamping the input voltage so as to prevent the input voltage from rising above the upper rail voltage. A second clamping transistor is coupled to the input for clamping the input voltage so as to prevent the input voltage from dropping below the lower rail voltage. Gain stages control the clamping transistors in response to the upper and lower threshold bias voltages and the input voltage so as to cause the clamping transistors to clamp the input voltage.