Dual-gate insulated gate field effect device

Abstract

A dual-gate insulated gate field effect device (1) such as a MOS tetrode has an active device area (3) in which adjacent source regions (5) are separated by and spaced apart from an intervening drain region (6) to define a respective conduction channel region (7) between each source and drain region (5 and 6). An insulated gate structure (10) has first insulated gate sections (11) forming an inner insulated gate (110) connected so as to surround each drain region 6 and second insulated gate sections (12) provided between the first insulated gate sections (11) and the source regions (5) and forming an outer insulated gate (120). Ends (11a,12a) of the insulated gate sections (11 and 12) extend onto the surrounding field oxide (4) to connect with respective first and gate conductors (13 and 14). Each drain region (6) is associated with an additional source region (50) spaced apart from the drain region (6) in a direction parallel to the width W of the conduction channel regions to define an additional conduction channel region. The second insulated gate sections (12) are connected to provide an area of insulated gate (12b) between each additional source region (50) and the associated drain region (6). This substantially eliminates leakage currents and enables the use of a design in which parasitic capacitances are reduced.