The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 18, 1996

Filed:

Feb. 22, 1995
Applicant:
Inventors:

Takayuki Shimada, Ikoma-gun, JP;

Toshihiro Yamashita, Yao, JP;

Yasuhiro Matsushima, Kashihara, JP;

Yoji Yoshimura, Nara, JP;

Yutaka Takafuji, Nara, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
257 72 ; 257369 ; 257351 ; 257372 ; 257 66 ; 257401 ;
Abstract

A thin-film semiconductor device having a CMOS inverter comprising a pair of n-type and p-type thin-film transistors, wherein the gate electrode of at least one of the paired thin-film transistors comprises a plurality of gate electrode sections spaced apart along the channel length. The channel region of the n-type thin-film transistor is doped with p-type impurities. This structure serves to reduce the leakage current and maintain high OFF resistance for a high source-drain voltage. Further, since a good symmetry of characteristics is maintained between the n-type and p-type thin-film transistors that constitute the CMOS inverter, no appreciable bias is caused in the output voltage of the CMOS inverter.


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