Variable accuracy indirect addressing scheme for simd multi-processors

Abstract

In a parallel processing architecture following the Single Instruction stream Multiple Data stream execution paradigm where a controller element is connected to at least one processing element with a local memory having a local memory address shift register adapted to receive and retain therein a globally broadcast memory base register address value received from the controller element for use by the processing element for access and transfer of data between the processing element and its respective local memory, a computer architecture for implementing indirect addressing and look-up tables includes a processing element shift register associated with the at least one processing element and adapted to receive and retain therein a local memory offset address value calculated or loaded by the associated processing element in accord with a first predetermined set of instructions. The processing element shift register transfers its contents bitwise to the local memory shift register of the local memory associated with the processing element, with the bit value of the most significant bit position being sequentially transferred to the least significant bit position of the local memory shift register in accord with a second predetermined set of instructions. A parallel transfer of the contents of the two shift registers is also disclosed.