Nonvolatile semiconductor memory device

Abstract

Disclosed is a nonvolatile semiconductor memory device, including a semiconductor substrate; an insulation layer located on the semiconductor substrate; and a plurality of memory cells arranged on the semiconductor substrate in a matrix with the insulation layer therebetween. The memory cells each includes a floating gate located on the semiconductor substrate with the insulation layer therebetween, a control gate for forming a capacitance with the floating gate with the insulation layer interposed therebetween, an impurity diffusion region located in the semiconductor substrate and having an opposite conductivity to that of the semiconductor substrate, and a bit line connected to the impurity diffusion region. The nonvolatile semiconductor memory device further includes an application device for applying a control voltage for reading data from the memory cell to the control gate; and a determination device for determining data to be read from a plurality of sets of data and outputting the data. The determination device determines the data to be read, based on the difference in voltages on the bit line in two different states of the memory cell. The difference in the voltages on the bit line is caused by the difference in the capacitances between the floating gate and the semiconductor substrate in the two different states of the memory cell. The difference in the capacitances is caused by the difference in charge levels in the floating gate when the control voltage is applied to the control gate in the two different states of the memory cell.