Bit field operating system and method with two barrel shifters for high

Abstract

A second barrel shifter whose shift amount is equally controlled as that of a first barrel shifter for shifting input data by an optional bit is employed as a mask data generating circuit in a bit field operational arithmetic unit. Areas with transistor trains of the first and second barrel shifters are formed in parallel to an area having the same width as that of a 1-bit storage cell of a register file and shift amount control lines in both barrel shifters are set for common use so as to reduce the area occupied by a chip. In order to increase the processing speed of extracting an optional area of data, the bit field operational arithmetic unit is provided with a circuit for subjecting all bits to signal expansion in No. 0 bit data in parallel to the shift of input data effected by the first barrel shifter. Moreover, barrel shift circuits include left and right shift circuits as n shift circuits for shifting 2.sup.i -bit (i=0, 1, 2, . . . , n-1) data, with n as a positive integer. Consequently, an optional number of bits up to 2.sup.n -bit of input data can thus be shifted by directing fetching n-bit shift control data.