The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 11, 1996
Filed:
Jun. 20, 1995
Applicant:
Inventor:
Gary P Powell, Allentown, PA (US);
Assignee:
AT&T Corp., Murray Hill, NJ (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364489 ; 364488 ;
Abstract
A method and system, in which the relative physical placement of configurable logic blocks, signal routing networks, and clock distribution trees of the FPGA implementation is preserved on the mask programmable logic cell (MPLC) substrate after the conversion process is completed. By constraining the physical placement of corresponding structures on the MPLC substrate at the network level of the MPLC implementation, the relative signal and clock delays presented during the FPGA implementation are substantially maintained in the MPLC implementation, thereby assuring functional equivalence between the FPGA and MPLC implementations.