The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 11, 1996
Filed:
Oct. 17, 1994
Paul J Fischer, Eau Claire, WI (US);
William G Petefish, Eau Claire, WI (US);
W. L. Gore & Associates, Inc., Newark, DE (US);
Abstract
An integrated circuit package for housing an integrated circuit (IC) chip and providing electrical connectivity of data signals and voltage signals between the IC chip and an electronic component includes a substrate, an IC chip affixed to the substrate and at least three conductive layers on the substrate. The three conductive layers include at least a first voltage layer adjacent to the substrate for providing a first reference voltage signal (i.e., ground) to the IC chip, a second voltage layer for providing a second reference voltage signal (i.e., power) to the IC chip, and a signal layer. To maximize speed and minimize complexing, all of the data signals to the IC chip are routed on the signal layer. The power and ground layers are closely coupled and separated by a dielectric layer having a relatively high dielectric constant for providing significant decoupling capacitance. A low dielectric layer is provided for separating the power layer from the signal layer. A plurality of electrical connections interconnect bonding pads on the IC chip with the electronic component (e.g., a PCB) by way of at least one of the conductive layers.