The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 11, 1996
Filed:
Feb. 23, 1994
Stanley Perino, Colorado Springs, CO (US);
Sanjay Mitra, Colorado Springs, CO (US);
Ramtron International Corporation, Colorado Springs, CO (US);
Abstract
Ferroelectric capacitors in an integrated memory are renewed to improve retention performance. The renewal method is performed on a wafer containing ferroelectric memory die. In one method, a rejuvenation anneal is performed after all electrical tests, including those at elevated temperatures, have been accomplished, but before the failed die have been inked. The rejuvenation anneal is performed at or above the Curie temperature of the ferroelectric material. In the preferred embodiment, the ferroelectric material is PZT, and the rejuvenation anneal is a thermal treatment at 400.degree. Centigrade in a nitrogen flow of roughly ten liters per minute for about an hour. In another method, separate electrical cycling and depoling operations are performed to provide the equivalent benefits of the single rejuvenation anneal. The electrical cycling operation is accomplished by writing about one hundred cycles at five volts alternating logic states into each ferroelectric capacitor into the array. The electrical cycling operation restores the symmetry and location of the hysteresis loop. The ferroelectric capacitor is then returned to the virgin state by a depoling operation. The electrical depoling operation is achieved by writing each capacitor in the array to a logic one and a logic zero at the full five volt power supply level initially, and then repeating each write cycle at decreasing power supply levels. The writing cycles are continued until the power supply is reduced to a minimum functional level and the polarization on the capacitors has been substantially removed.