Coherency for write-back cache in a system designed for write-through

Abstract

A write-back coherency system is used, in an exemplary embodiment, to implement write-back caching in an x86 processor installed in a multi-master computer system that does not support a write-back protocol for maintaining coherency between an internal cache and main memory during DMA operations. The write-back coherency system interrupts the normal bus arbitration operation to allow export of dirty data, and includes an X%DIRTY latency-control function. In response to an arbitration-request (such as HOLD), if the internal cache contains dirty data, the processor is inhibited from providing arbitration-acknowledge (such as HLDA) until the dirty data is exported (the cache is dynamically switched to write-through mode to prevent data in the cache from being made dirty while the bus is arbitrated away). While the requesting bus master is accessing memory, bus snooping is performed and invalidation logic invalidates at least those cache locations corresponding to locations in memory that are affected by the requesting bus master. The X%DIRTY function provides write-back latency control by dynamically switching the cache from write-back to write-through mode if a cache write would cause the number of cache locations containing dirty data to exceed a predetermined maximum percentage of the total number of cache locations.