Ic semiconductor memory devices with maintained stable operation and

Abstract

Semiconductor memory devices, such as, SRAM IC memory devices, include a shield structure for shielding load elements in the memory cells of the memory devices from electric fields generated by surrounding active or passive elements, such as, an underlying MOSFET or a voltage supplying interconnect, to prevent deterioration of the operational resistance values and characteristics of the load elements. In the case of resistance elements utilized as load elements, a partial shield structure, i.e., a shield layer, at a constant voltage or zero volts, spatially underlying only a portion of the length of the resistance element is adequate to substantially remove the effect of such electric fields. In the case of TFT channel devices having channel offset regions utilized as load elements, a shield structure, i.e., a shield layer spatially underlying the TFT channel offset region is adequate to substantially remove the effect of such electric fields. In the case of a p-channel TFT, the shield is set at a constant voltage and in the case of a n-channel TFT, the shield is set at zero volts. The use of such shield structures permits decrease in the consumption current during waiting or OFF time conditions of the memory cell operation so that overall current consumption in operation of the memory device is significantly decreased.